A method is known in which capacitive elements are formed in an LSI comprising MISFETs that compose circuits, by utilizing the gate oxide films of the MISFETS. To use the capacitance of the gate oxide film of each MISFET, the storage region of a p-channel MISFET or the inversion region of an n-channel MISFET is utilized.
The Japanese Patent Application Laid-open Publication No. 61-232656 discloses the technique of forming a MOS-type capacitive element at the same time the thin gate oxide film of a nonvolatile memory element is formed, thereby to reduce the area of the MOS-type capacitive element. This technique has been devised in view of the fact that the electrode of a MOS-type capacitive element is necessarily large if the insulating film of the MOS-type capacitive element is formed at the same time the gate oxide film of an ordinary MOSFET is formed, because the gate oxide film of the MOSFET is relatively thick.
The Japanese Patent Application Laid-Open Publication No. 5-235289 discloses an LSI in which the MOS-type capacitive elements are used in an inversion region over the entire input voltage range by controlling the threshold voltage (Vth) of the MOS-type capacitive elements. The LSI has been proposed in consideration of the fact that a conventional MOS-type capacitive element that uses the storage region has its operating characteristic greatly influenced if the operating power-supply voltage is lowered as required to minimize the power the LSI consumes.